Delay Minimization for Zero-Skew Routing

Delay minimization methods are proposed for zero-skew routings. A delay-time estimation formula is derived, which can be used as an objective function to be minimized in zero-skew routing algorithms. Moreover, the optimum wire width is formulated. Experimental results show that our methods with a clustering-based algorithm achieve 50% reduction of the delay time on benchmark data with 3000 pins. 1 Department of Computer Science, Princeton University and C&C Systems Research Laboratories, NEC Corporation 1 Introduction With the increase of the clock rate in VLSI, the clock-net routing scheme plays more critical roles. In order to make the clock rate higher, at least two factors should be taken into account in clock-net routing. First, since the clock skew affects the clock period directly, exact zero skew is desired. Next, the delay time should be minimized in a clock net. Consider an example of single-phase clocking in Fig. 1. In CMOS design, the delay time is dominated by the rise/f..