Performance Analysis and Optimization of Latency Insensitive Systems

Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary variations in interconnect latency. However, this approach does not guarantee the same robustness for the performance of the design, which indeed can experience big losses. This paper presents a simple, yet rigorous, method to (1) model the key properties of a latency insensitive system, (2) analyze the impact of interconnect latency on the overall throughput, and (3) optimize the performance of the final implementation. 1 Introduction As system complexity increases and market windows continue to shrink, effective reuse of existing designs or Intellectual Property (IP) cores seems the only way to produce a reliable design within a reasonable time [8, 20]. In fact, most semiconductor companies share both a strong will to broaden IP reuse and an open complaint towards the effectiveness of the tools offered by the ED..