Comparitive Study Of Diffrent Multiplier Architectures

Abstract—- This paper presents a comparative analysis of three different multiplier architectures. The three multipliers architecture are array multiplier, a column bypass multiplier, and a array multiplier using Reversal Logic schemes. The multipliers are implemented on Spartan 6 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area. The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of the three multipliers has its own trade-offs between power and delay. decreases the ability of minimize the power dissipation based on bypass extra bits to next steps.. II RELATED WORK The multiplication method for an N bit multiplicand by M bit multiplier is shown below