Design of Area-Delay Efficient VLSI Architecture for Multilevel 2D DWT

Abstract: This project presents a concept to solve the computational complexity for efficient realization of 2D DWT in VLSI application. For this purpose, the proposed design scheme introduced a Memory efficient architecture for multilevel 2D DWT using a generic structure 3(K-2) M/4, where K is the order of the filter and M is the image height. The proposed operation is based on Daubechies as well as biorthogonal filters and the structure does not involve frame-buffer. It involves line-buffers which is independent of throughput rate. The main advantage of this work is reduced Area Delay Product(ADP) and Energy Per Image(EPI).The concept can also highlight the independency of throughput which makes it convenient for higher application. The proposed structure can provide regular data flow, small cycle period(Tm) and 100 % hardware utilization efficiency. Index terms—2-D discrete wavelet transform (DWT), DWT, lifting, systolic array, very large scale integration (VLSI). 1