Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga

Monte Carlo (MC) method is widely applied in mathematical problems that are extremely complicated to be resolved analytically. The method involves sampling process of the random numbers and probability to estimate the result. Since it depends on an enormous number of good quality random numbers to produce a high accuracy result, developing a good random number generator (RNG) is vital. Generally, the RNGs and the MC methods are implemented in software-based and simulated using supercomputer and cluster Personal Computer (PC). Nevertheless, this implementation consumes large expenses and inefficient space. With the latest improvement of the density and speed of Field Programmable Gate Arrays (FPGA), a direct implementation onto this hardware is feasible. This work aims to implement the RNG and MC method of Random Walk on the Boundary (WOB) to compute the unit cube capacitance on the target device Xilinx Spartan-6 LX 150T FPGA which were incorporated in Avnet S6LX150T development board. Four uniform RNGs model were evaluated to build the RNG, and the model that produced the most accurate computation result was chosen for the implementation. From the evaluation, the result has demonstrated that the RNG built from uniform RNG of 43-bit Linear Feedback Shift Register (LFSR) and 37-bit Cellular Automata Shift Register (CASR) uniform RNG combination produced the most accurate computation result. The implementation of the MC computation and RNG to compute the unit cube capacitance has been successfully carried out on the Xilinx Spartan-6 LX 150T FPGA. It therefore demonstrates the feasibility of the FPGA as another hardware alternative for this kind of work