Implementing and Comparing Static and Machine-Learning scheduling Approaches using DPDK on an Integrated CPU/GPU

As 5G is getting closer to being commercially available, base stations processing this traffic must be improved to be able to handle the increase in traffic and demand for lower latencies. By utilizing the hardware smarter, the processing of data can be accelerated in, for example, the forwarding plane where baseband and encryption are common tasks. With this in mind, systems with integrated GPUs becomes interesting for their additional processing power and lack of need for PCIe buses.This thesis aims to implement the DPDK framework on the Nvidia Jetson Xavier system and investigate if a scheduler based on the theoretical properties of each platform is better than a self-exploring machine learning scheduler based on packet latency and throughput, and how they stand against a simple round-robin scheduler. It will also examine if it is more beneficial to have a more flexible scheduler with more overhead than a more static scheduler with less overhead. The conclusion drawn from this is that there are a number of challenges for processing and scheduling on an integrated system. Effective batch aggregation during low traffic rates and how different processes affect each other became the main challenges