A Low-Power Standard Cell Library for Cryogenic Operation

With the advances towards a quantum computer incorporating many qubits, the demand for a scalable readout and control platform rises. Recent proposals for such a platform exploit the maturity of CMOS technology, to implement the various analog, RF and digital circuits required. To allow for scaling, the electronics that constitute this platform are translated close to the qubits in a cryogenic environment. Limited power dissipation can be absorbed in this environment, stressing the need for low-power circuits. Presently, digital control is carried out by FPGAs due to the rapidly changing control parameters. FPGAs are expected to be replaced in the future by ASICs, as they are inferior in terms of performance, area and most critically power dissipation. Conventional standard cells used for digital ASIC implementation are expected to be sub-optimal with respect to low-power and cryogenic operation, due to a shift in device characteristics in this environment. This thesis proposes the first minimal standard cell library designed for this environment, with low-power operation in mind, that enables future digital and mixed-signal designs to address the requirements demanded by the cryogenic environment