Synchronization mechanisms and analysis for real-time systems on FPGA-based heterogeneous platforms

Motivated by the increasing computational demands of application workloads in the field of cyber-physical systems, computer architectures are evolving towards heterogeneous platforms consisting of hybrid computational devices that integrate general-purpose multiprocessors with specialized hardware accelerators such as FPGAs and GPUs. In particular, the dynamic partial reconfiguration (DPR) capabilities offered by modern FPGA devices enable the possibility of scheduling the concurrent execution of multiple hardware functions on an FPGA that is shared by different processing components. The aim of this thesis is to derive a suitable system model and real-time analysis for heterogeneous platforms consisting of a multiprocessor system combined with a DPR-enabled FPGA, thus enabling time-predictable hardware multitasking of accelerated functions in modern heterogeneous platforms. The concurrent execution of hardware functions on the FPGA is managed by a specialized scheduling infrastructure that resolves contention on the FPGA slots and on the FPGA reconfiguration interface guaranteeing a starvation-free progress mechanism, which is fundamental in a time-critical scenario. Concurrent access to shared hardware functions by software activities running on different processors is protected using the P-FMLP+ real-time multiprocessor locking protocol, which ensures asymptotic optimality in terms of maximal amount of blocking time in the access to shared resources