DESIGN FLOW OF ADVANCED ENCRYPTION STANDARD HARDWARE ACCELERATION USING ZYNQ SYSTEM-aN-CHIP

The Advanced Encryption Standard (AES) is a symmetric encryption algorithm used by the United States government to protect sensitive information. In this study, three implementations of a 256-bit AES algorithm are presented to accelerate the computational elements of the algorithm: a low-area, high-performance, and hybrid implementation. The three implementations were developed for the ZedBoard development board which contains a Zynq-7000 SoC. The Zynq-7000 SoC contains both a processing system (dual-core ARM processor) and programmable logic (Xilinx-7 FPGA). This relation between hardware and software of the Zynq-7000 SoC was exploited by implementing the key schedule algorithm of AES on the dual-core ARM processor, while implementing the AES encryption core on the Xilinx-7 FPGA. A high-level synthesis design flow was followed for its flexibility and reduction of development time. The result for latency is about a 2.5 times acceleration for the low-area implementation, a 12 times acceleration for the hybrid implementation, and a 44 times acceleration for the high-performance implementation. For the area results, the high-performance implementation can theoretically fit 13 encryption cores on the ZedBoard, while both the low-area and hybrid implementations can theoretically fit 35 encryption cores on the ZedBoard.M.S. in Computer Engineering, May 201