HARDWARE ACCELERATION OF HASHING FUNCTIONS FOR CRYPTOCURRENCY MINING USING ZYNQ SOC

Cryptocurrencies rely on secure hashing algorithms and public key cryptography to keep transactions secure, disallow double spending, and keep a decentralized ledger. In a bitcoin’s lifetime, the most computationally intensive work is done at conception. New bitcoins are brought into the ecosystem by a process named mining. While mining encompasses various mathematical functions and nuances that will be described in this thesis, the key element is a double SHA256 function, which has to be performed many times until the specified criterion is met. The focus in this thesis will be to speed up one iteration of this double hash function by making optimizations in hardware. The hashing function along with its optimizations will be implemented on Xilinx’s Zedboard, which contains both an FPGA chip as well as a microprocessor (ZYNQ7). Using Xilinx’s product suite, the double hashing function was taken from a high abstraction level language to low-level hardware deployment, following the design flow and applying various optimization methods, or directives. Some of the methods employed were array partitioning, pipelining, and loop unrolling. The primary goal in this thesis is not to simply achieve low latency; rather it is to reach a compromise between latency, power consumption, and area usage. Techniques are explored and tested both individually and in hybrid solutions and various practical tradeoffs are considered. Miners have to take into account the associated increase in hardware and power costs that come with high-area hardware implementations. After all, a miner is not going to want a setup that costs more to run than the worth of the Bitcoins mined. Therefore, the focus in this thesis is to optimize the double SHA256 hashing function for speed, area, and power. The work done has pointed towards array partitioning – a technique that brings frequently accessed variables from BRAM into registers. It allows for the best combination of decreased latency with only marginal increases in power and area. Utilized alongside pipelining, in tests, a speedup of 2.83x was achieved over an auto-optimized hardware implementation while decreasing both power consumption and the usage of look-up tables (LUTs) and flip-flops (FFs). Implementing these optimizations into a real-life mining rig, complete with comparator, incrementing nonce, and live block header construction has been left as future work. In addition, optimizing various other mathematical functions of the Bitcoin life cycle lies beyond the scope of this thesis. As such, this work serves to reduce latency for a single iteration of the double SHA256 function as it applies to Bitcoin mining, while taking into account practical considerations for the miner. The result is an IP core that can be instantiated 10-15 times in a modest FPGA chip and used in the development of a full mining rig.M.S. in Electrical Engineering, May 201