SRAM DESIGN BASED ON CNFET: A DISCUSSION ON CIRCUIT, PARAMETER AND DIAMETER VARIATION

This thesis describes the effort in designing SRAMs based on Carbon Nanotube Field Effect Transistor (CNFET), and covers several aspects including circuit structure, parameters, layout and the detection of diameter variation. It aims at providing a primitive reference on the topic of employing CNFETs in realistic SRAM design. In this thesis, we propose a guideline for choosing appropriate transistor ratios with respect to differently selected diameters in a conventional 6-T SRAM. Constraints of transistor ratios are established, followed by the optimization of the ratios regarding Static Noise Margin (SNM) and Read Noise Margin (RNM) of the cell. With the optimal parameters, the CNFET cell can achieve 41.41% and 1.26% improvement over traditional CMOS in SNM and RNM, respectively. Then we propose a column-based monitoring circuit which is capable of detecting variation in the diameter of tubes. It is grounded on a novel layout of the 6-T SRAM based on CNFET, which assigns all cells in a column of the SRAM array to the same group of Carbon Nanotubes (CNTs). This monitor outputs a digital signal indicating the impact of diameter variation on delay of the circuit, and enables further mitigation of the variation. Alternatively, a new 6-T SRAM cell structure is proposed for optimizing the performance of the cell at very-low or sub-threshold supply voltages. Compared with a traditional 6-T cell, simulation results show that the reading and writing delay have been improved by more than 80% and 75% at 0.4V supply voltage, respectively. It achieves PDP reduction of 70% and 91% for reading and writing operations.M.S. in Electrical Engineering, May 201