CHARGE PUMP AND LOOP FILTER IN A GHZ PHASE LOCKED LOOP DESIGN

Mobile and portable devices are becoming more and more prevailing in these years, and this makes the demands of portable telecommunication systems such as smart antennas and other phased array systems, becoming more and more important. CMOS mixed-signal design is pretty popular in today’s Radio Frequency Integrated Circuits industry for the low cost and great performance. This article is aimed to design a CMOS frequency synthesizer, in here is a Charge Pump Phase Locked Loop, and it is used to test the high speed, mixed-signal CMOS circuit design skills of the designer. The project is under usage of 65nm TSMC CMOS process technology, which is deep sub-micron technology, thus issues such as noise rejection, high frequency parasitic effects, overall efficiency, leakage current, power dissipation, etc. can be exposed and the designer’s problem solving skills can be exercised and examined. This work presents the detailed design and measurement results for a phase synthesizer using Charge Pump PLLs for achieving phase shift in the range of ±180°. Several Charge Pump PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability. Commercial applications in the ZigBee (with basic of IEEE 802.15.4) band motivate this design of a Charge Pump Phase Locked Loop system in 915 MHz band in USA, since ZigBee is with 868 MHz in Europe, 915 MHz in the USA and Australia, and 2.45 GHz in most jurisdictions worldwide. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations shall be used to verify the logic behavior performance. The transistor level design of every block is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial modeling analysis and improved iteratively. The Charge Pump, the Loop Filter and the VCO of the PLL system is implemented in TSMC 65nm CMOS process and consumes 0.5 of power from a 1.2V power supply with a settling time of 39.40 ns.M.S. in Electrical Engineering, December 201