Decimal Multiplication Architecture for FPGA Implementation

The hardware support for the Decimal Multiplication is gaining importance in commercial applications including banking, accounting, tax calculations, currency conversion and insurance. In this work, we examine the di erent types of number sys- tems that have been used for executing Decimal Multiplication. A unique signed-digit representation is used for reduced logic and latency. Furthermore, partial product ac- cumulation is performed with Svoboda decimal adder, which is e cient. The imple- mentation of the proposed architecture is modeled using VHDL and then synthesized on FPGA. The hardware resources for this architecture are analyzed. This work presents an important case study for FPGA implementation of Decimal Arithmetic architectures such as ALUs.M.S. in Electrical Engineering, July 201