Investigation of Sequential Machine Design Techniques for Implementation of a TRAC Scanning Algorithm

This report will demonstrate the design techniques to translate a given scanning algorithm into a hardwired pre-processor. The language to be pre-processed is TRAC (Text Reckoning and Compiling) devised by Mooers and Deutsch. The major drawback in the current implementation of TRAC is speed. The software overhead required for string manipulations and execution of the input scanning algorithm is the major degrading factor. A TRAC machine consisting of a hardwired pre-processor to scan the input and produce formatted data for a stack oriented evaluator is proposed. The control machine for the input scanning algorithm for the pre-processor is designed using various sequential machine design techniques. The one-hot code and the minimum state variable design represent the two extremes which are presented