Add to ORKGA circuit analysis of the BiCMOS switching transient is presented. The BiCMOS pull-up delay as a function of transistor parameters and power supply voltage is evaluated. The analytical predictions are compared with SPICE circuit simulation. Good agreement between the model and SPICE simulation is obtained. Two-dimensional numerical device simulation is used to examine the physical insight into BiCMOS device operation
A novel methodology for modeling the effects of process variations on circuit delay performance is p...
This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gate...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
A circuit analysis of the BiCMOS switching transient is presented. The BiCMOS pull-up delay as a fun...
Temperature-dependent BiCMOS gate delay analysis including high current transient has been developed...
The BiNMOS gate delay analysis including high current transients has been developed. The modeling eq...
An alternative switching delay reduction technique for CMOS & BiCMOS digital circuits is examined. A...
The BiNMOS gate delay analysis including high current transients has been developed. The modeling eq...
A non-iterative formula is derived for calculating the delay time of digital BiCMOS circuits with th...
The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT de...
The effect of ionising radiation on the BiCMOS switching response has been studied. The radiation-in...
A technique for modeling the effect of variations in multiple process parameters on circuit delay pe...
The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It i...
This thesis is concerned with optimising BiCMOS circuits. A numerical optimiser finds the set of arg...
Design closure in today\u27s advanced chip construction requires a delicate balance among various co...
A novel methodology for modeling the effects of process variations on circuit delay performance is p...
This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gate...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...
A circuit analysis of the BiCMOS switching transient is presented. The BiCMOS pull-up delay as a fun...
Temperature-dependent BiCMOS gate delay analysis including high current transient has been developed...
The BiNMOS gate delay analysis including high current transients has been developed. The modeling eq...
An alternative switching delay reduction technique for CMOS & BiCMOS digital circuits is examined. A...
The BiNMOS gate delay analysis including high current transients has been developed. The modeling eq...
A non-iterative formula is derived for calculating the delay time of digital BiCMOS circuits with th...
The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT de...
The effect of ionising radiation on the BiCMOS switching response has been studied. The radiation-in...
A technique for modeling the effect of variations in multiple process parameters on circuit delay pe...
The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It i...
This thesis is concerned with optimising BiCMOS circuits. A numerical optimiser finds the set of arg...
Design closure in today\u27s advanced chip construction requires a delicate balance among various co...
A novel methodology for modeling the effects of process variations on circuit delay performance is p...
This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gate...
UnrestrictedThis dissertation investigates the effect of capacitive crosstalk on interconnect and lo...