Delay Analysis Of Binmos Driver Including High-Current Transients

The BiNMOS gate delay analysis including high current transients has been developed. The modeling equations account for high electric field effect in the nMOS transistor and emitter crowding, base pushout, and base conductivity modulation in the bipolar transistor. In examining the switching transient of a BiNMOS driver, base pushout mechanism exhibits the detrimental effect on the gate propagation delay. The present circuit modeling methodology provides a fast turn-around design evaluation of sensitivity of process and device parameters into circuit performance. Computer simulation of a BiNMOS driver using the present analysis is compared with PISCES device simulation in support of physical reasoning