A Comparison of FIRSTSIM and VHDL for the Description and Simulation of Concurrent Systems

Block diagram descriptions are common in the design, development and simulation of engineering systems. In concurrent systems, both parallel and pipelined, facilities for specifying the transformations associated with new blocks or processes, the replication and tailoring of pre-defined blocks, and the communication, control and monitoring of blocks are important features in the selection of a language for description, simulation and analysis. This thesis investigates and compares two languages which have many of the above attributes, VHDL (VHSIC Hardware Description Language) and FIRSTSIM (FIRST Simulator). FIRSTSIM was designed at the University of Central Florida using ADA, a general purpose high-level programming language and was applied to bit serial digital signal processing in a silicon compiler environment. VHDL is an IEEE (Institute of Electrical and Electronics Engineers) and DoD (Department of Defense) standard description language with a support environment which is targeted to support ASIC (Application Specific Integrated Circuits) development and has a wide range of features for technology insertion in the VHSIC (Very High Speed Integrated Circuits) environment