科研費報告書収録論文(課題番号:13558026・基盤研究(B)(2)・13～16/研究代表者:羽生, 貴弘/転送ボトルネックフリー多値ロジックインメモリVLSIの開発と応用
This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of ...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
Multiple-valued logic (MVL) circuits propose a number of possible improvements to current VLSI circu...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
In this paper are proposed new many-valued gates K-PLA, T(2/K) and T(K/2) for a logical synthesis of...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits...
Abstract: A three-level programmable logic array (three-level PLA) consists of three main parts, the...
A method for designing PLA-based combinational circuits by modular decomposition is presented. Main ...
We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits...
AbstractA voltage-mode three transistor based MAX circuit for implementation of multi-valued logic (...
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibilit...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
AbstractIn this paper we propose a new technique for designing easily testable PLAs. Our design is a...
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable ...
This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of ...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
Multiple-valued logic (MVL) circuits propose a number of possible improvements to current VLSI circu...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
In this paper are proposed new many-valued gates K-PLA, T(2/K) and T(K/2) for a logical synthesis of...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits...
Abstract: A three-level programmable logic array (three-level PLA) consists of three main parts, the...
A method for designing PLA-based combinational circuits by modular decomposition is presented. Main ...
We propose the use of universal literals as a means of reducing the cost of multiple-valued circuits...
AbstractA voltage-mode three transistor based MAX circuit for implementation of multi-valued logic (...
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibilit...
Multiple-valued logic (MVL) circuits can be designed and implemented, utilizing 4 levels of logic, i...
AbstractIn this paper we propose a new technique for designing easily testable PLAs. Our design is a...
Over the last two decades, design using Multiple-Valued Logic (MVL) has been receiving considerable ...
This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of ...
科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用
Multiple-valued logic (MVL) circuits propose a number of possible improvements to current VLSI circu...
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