Architecture of Micro Energy Harvesting Using Hybrid Input of RF, Thermal and Vibration for Semi-Active RFID Tag

This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device.This research work presents a novel architecture of Hybrid Input Energy Harvester (HIEH) system for semi-active Radio Frequency Identification (RFID) tags. The proposed architecture consists of three input sources of energy which are radio frequency signal, thermal and vibration. The main purpose is to solve the semi-active RFID tags limited lifespan issues due to the need for batteries to power their circuitries. The focus will be on the rectifiers and DC-DC converter circuits with an ultra-low power design to ensure low power consumption in the system. The design architecture will be modelled and simulated using PSpice software, Verilog coding using Mentor Graphics and real-time verification using field-programmable gate array board before being implemented in a 0.13 µm CMOS technology. Our expectations of the results from this architecture are it can deliver 3.3 V of output voltage, 6.5 mW of output power and 90% of efficiency when all input sources are simultaneously harvested. The contribution of this work is it able to extend the lifetime of semi-active tag by supplying electrical energy continuously to the device. Thus, this will indirectly  reduce the energy limitation problem, eliminate the dependency on batteries and make it possible to achieve a batteryless device