Simulation Studies Of 30 MHz Phase-Locked Loop Coherent Receiver

Phase-Locked Loop or in short PLL is a vital part in electronics system mainly in communication system in getting back the transmitted signal. As a whole, it is basically a closed loop frequency control system where its function is based on the phase sensitive detection of phase difference between the input signal (transmitted signal) and the output of the controlled oscillation. Although the system had been around since 1930's, implemented by the French Engineer, H. De Bellescise~ but still, until today further development is in progress in achieving better response and performance in retrieving and synchronising transmitted signals. The purpose of this project is to familiarise in designing and constructing a 30 MHz Phase-Locked Loop Coherent Receiver by computer simulation, taking account the requirements for each building block of a PLL system, the stability of the system and the response of the system. To achieve this, the process includes simple and direct calculations, and circuit simulations observation. Results are represented in graphs and are analysed