This paper is focused on the latency and power dissipation in clock systems, which should be lower when the optical interconnects are applied. Simulation shows that the power consumed by an optical system is lower than that consumed by an electrical one, however the advantages of optics drastically decrease with the number of output nodes in H-tree. Additionally, simple replacement of an electrical system by an optical clock distribution network (CDN) results in high clock skew, which will be higher than 10% of the clock period for the 32 nm technology node
As communications data traffic continues to increase, electronic interconnects over short reaches ar...
Abstract-The evolution of integrated circuit technology is causing system designs to move towards co...
As technology scales, the device delay decreases while the interconnect delay increases. As more dev...
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasing...
Abstract: CMOS is arguably the most successful semiconductor technology in electronics history. This...
Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a ...
Clock distribution has become an increasingly challenging problem for VLSI designs, consuming an inc...
Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with ...
The evolution of integrated circuit technology is causing system designs to move towards communicati...
Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The fun...
Optics potentially addresses two key problems in electronic chips and systems: interconnects and tim...
The various arguments for introducing optical interconnections to silicon CMOS chips are summarized,...
VLSI/ULSI and the evolutions being driven by the International Technology Roadmap for Semiconductors...
Cette thèse vise à définir les challenges que les solutions optoélectroniques devront relever pour r...
Electrical interconnects are becoming a bottleneck in the way towards meeting future performance req...
As communications data traffic continues to increase, electronic interconnects over short reaches ar...
Abstract-The evolution of integrated circuit technology is causing system designs to move towards co...
As technology scales, the device delay decreases while the interconnect delay increases. As more dev...
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasing...
Abstract: CMOS is arguably the most successful semiconductor technology in electronics history. This...
Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a ...
Clock distribution has become an increasingly challenging problem for VLSI designs, consuming an inc...
Clock is regarded as the heartbeat of modern synchronous digital integrated circuits. However, with ...
The evolution of integrated circuit technology is causing system designs to move towards communicati...
Clock Distribution Network (CDN) is an important component of any synchronous logic circuit. The fun...
Optics potentially addresses two key problems in electronic chips and systems: interconnects and tim...
The various arguments for introducing optical interconnections to silicon CMOS chips are summarized,...
VLSI/ULSI and the evolutions being driven by the International Technology Roadmap for Semiconductors...
Cette thèse vise à définir les challenges que les solutions optoélectroniques devront relever pour r...
Electrical interconnects are becoming a bottleneck in the way towards meeting future performance req...
As communications data traffic continues to increase, electronic interconnects over short reaches ar...
Abstract-The evolution of integrated circuit technology is causing system designs to move towards co...
As technology scales, the device delay decreases while the interconnect delay increases. As more dev...