On the Implementation of Low Power Pipelined FFT Processor for UWB Communication Systems

The availability of enormous bandwidth, the potential for high data rates, and the promise for small size and low processing power with reduced implementation cost, all present a unique opportunity for Ultra Wide Band (UWB) to become a widely adopted radio solution for future wireless home networking technology so called Wireless Personal Area Networks (WPANs). The Orthogonal Frequency Division Multiplexing (OFDM) approach has been a leading proposal for the IEEE 802.15.3a WPAN standard and has been approved as the UWB standard by the European Computer Manufacturers Association (ECMA). The very high data sampling rate up to 528Msample/s or more poses a challenge to realize the physical layer of the UWB system, particularly the components with high computational complexity implemented in Very Large Scale Integration (VLSI). The present paper deals with the VLSI implementation of such a computationally complex and low power FFT (Fast Fourier Transform) processor, which is a critical block in all multi-carrier systems used primarily in the mobile communication. A low power pipelined SDF (Single Delay Feedback) radix-2 FFT architecture is presented here to meet the portability requirement of these systems. FFT processor has been simulated and implemented on Xilinx Spartan-3A DSP1800A FPGA (Field Programmable Gate Array)