Architectural Design and Implementation of Bit Error Rate Tester on FPGA

FPGAs have witnessed an increased use of dedicated communication interfaces. With their increased use, it is becoming critical to test and properly characterize all such interfaces. Bit error rate (BER) characteristic is one of the basic measures of the performance of any digital communication system. This thesis presents a scheme for BER testing in FPGAs, with a few orders of magnitude speedup compared to other tradition methods. Where the using of hardware emulation by FPGA is very interested for most researches and designers in present time, because it has properties such as flexibility in reprogramming it and prepare it according to the user need, so we chose this technique in this thesis as an implementation environment to the proposed scheme. The proposed scheme mainly consists of an essential scheme core: a bit error rate tester (BERT), by using MATLAB Simulink software in the beginning, then composition this software on FPGA chip (spartan-6 type) by using ISE 14.2 software. The results shows very good agreement between software representation and the implementation on FPGA chip