Facilitating Fault-Simulation Comprehension through a Fault-Lists Analysis Tool

The complexity of modern embedded processors used in safety-critical applications requires in-field self-test strategies. The most popular ones are based on hardware and software-based approaches such as Logic-BIST (L-BIST) and Software-Based Self-Test (SBST). While the first one requires to include in the device additional hardware, the second consists on the execution of a set of assembly programs, usually called a Software Test Library (STL). In this context, in case the STL strategy is adopted for in-field testing of the device, a very time consuming task is necessary to validate the final results of the test library. This process includes fault simulation for every test program and aims at determine the actual contribution that a given test may provide to the final test library, by manipulating intermediate results, comparing, including, and excluding the test program results with respect to all the others. This task is useful, for example, to understand whether the changes made to a test program produced a gain in the final fault coverage or not. In this paper, we propose for the very first time, a Fault List Analysis Tool that is able to support the development of a STL by performing some fault-list oriented operations on the preliminary results obtained during the development process. Some experimental results were gathered during the STL development for various industrial processor