Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems

Some industrial domains, characterized by particularly strict safety standards – e.g., avionics – are facing issues when addressing the usage of commercial-off-the-shelf multi-processor system-on-chips and in particular new network- on-chip-based architectures. One key issue is related to the usage of such system-on-chips to implement mixed-criticality systems with the main goal of reducing size, weight, and power consumption of on-board equipment by reducing the number of computers moving from federated architectures based on single- core processors to a single multi-core processor. To comply with relevant safety standards, a mixed-criticality system should be proven to enforce isolation among safety-critical and non-safety- critical tasks running on the multi-core hardware platform. This paper presents a software-level methodology tackling such issue. The proposed methodology exploits knowledge of the deterministic routing algorithm used by the network-on-chip to implement a safe and efficient partitioning of the system. This paper presents the software implementation and an experimental evaluation of the solution, proving its suitability for integration in an avionic application