Design of the Readout chip for CGEM Detector in BESIII Experiment

BEPC (Beijing Electron Positron Collider) is a large accelerator located in Beijing. BEPC aims mainly to study physics in the tau-charm centre-of-mass energy region (2– 4.6 GeV). With a maximum luminosity of 1.0×1033cm−2s−1, many physics topics have been discovered by the data taken from BEPC. As the most important assembly of BEPC, BESIII (Beijing Electron Spectrometer III) is an experimental spectrometer consisting of a group of detectors. The MDC is a cylindrical gas drift chamber located in the most inner part of BESIII. The main target of the MDC is to identify the particles, with a high spatial resolution. The CGEM-IT (Cylindrical Gas Electron Multiplier - Inner Tracker) project is proposed to replace the aged MDC, with a new CGEM detector, which is inspired by the GEM detector in the KLOE-II experiment, with some new innovations. To meet the requirement of the physics study, the CGEM detector is expected to have a spatial resolution better than 130 μm of the chamber. Due to the specific requirement of the CGEM readout electronics, the idea of designing an ASIC for the CGEM detector is proposed. Compared with the traditional readout electronics built with discrete devices on PCB board, the ASIC have much high integration, which has thus the advantages of smaller space occupation, lower power consumption, less cost, etc. Besides the classic modules which are commonly used in high energy experiments, like the preamplifier, shaper and discriminator, the ASIC can integrate more digital processing cells, making the ASIC an independent working system. The ASIC will target to meet the requirements of the detector, on aspects like the data rate, charge and time resolution, power consumption and so on. In this thesis, the design details of the readout ASIC of the CGEM detector will be discussed. The chip has 64 channels and integrates both analogue and digital circuits. In the analogue part, a low noise charge sensitive amplifier is applied, driving a fast shaper and a slow shaper to give the time stamp information and the charge information at the same time. Optimizations have been made to achieve a charge resolution of 1 fC and a time resolution of 5 ns. Both the time information and the charge information are effective for the spatial resolution of the detector. Under the condition with the maximum detector capacitance 100 pF, the chip is expected to have an ENC noise less than 2000 electrons. The charge measurement can be selected as TOT mode or QDC mode. In the digital part of the chip, a low-power TDC with a time resolution of 50 ps is implemented to digitize the TOT information. And when working in QDC mode, the TDC can be configured into a Wilkinson ADC to read out the charge information offered by a sample and hold circuit directly. Redundancy design has been implemented in the digital circuit to derandomize the signal to avoid the signal pile up and on the other hand, reduce the SEU (Single Event Upset) effect caused by the high radiation density inside BESIII. The chip has been fabricated with UMC 110 nm technology. The characterization of the chip is ongoing in the INFN laboratory in Turin, and the first joint measurement of the chip together with the CGEM detector has been done very recently in Ferrara. Preliminary results of the chip are given in this thesis