Hardware Design and Realization for Iteratively Decodable Codes

From the methodological point of view, the design of efficient channel decoders for wireless applications is an extremely difficult and exciting domain of practicing. In most of the cases, hardware design activity is abstracted from the addressed application, meaning that a set of area and performance constraints are extracted from the application and the digital designer can concentrate his attention onto hardwarespecific issues,which are largely independent of the application. The design of channel decoders requires a significantly different approach, where system and architecture levels are strictly interconnected and the hardware design activity cannot be separated from the deep knowledge of the underlying algorithms. Instead, decoding algorithms and hardware architectures must be jointly studied and optimized, having in mind that any choice at the implementation level has an impact on the system level performance and vice versa. Hardware aware algorithm simplifications and finite precision representation of both external and internal data are imperative to achieve area and energy efficiency, but their effect on communication performance must be carefully evaluated, usually by means of bit and cycle accurate software models and Monte Carlo simulations. The first section presents the standard implementation of a Turbo-Code decoder and that of an LPDC decoder, in order to fix the internal accuracy and the notations. The three next sections are dedicated respectively to area optimization, speed optimization and energy optimization. Section 5 dealswith the flexible implementation of iterative decoders. Section 6 explores non-standard decoding techniques (analog and stochastic decoders). Finally, Section 7 describes some relevant implementations