The generation of device drivers is a very time consuming and error prone activity. All the strategies proposed up to now to simplify this operation require a manual, even formal, specification of the device driver functionalities. In the system-level design, IP functionalities are tested by using testbenches, implemented to contain the communication protocols to correctly interact with the device. The aim of this paper is to present a methodology to automatically generate device drivers from the testbench of any RTL IP. The only manual step required is to tag the states corresponding to the different device functionalities. The Extended Finite State Machines (EFSMs) are then used to create a correct-by-construction two-level device driver:...
With the rapid increase in the complexity of digital circuits, the design abstraction level has to g...
Due to the character of the original source materials and the nature of batch digitization, quality ...
In this paper, we present a technique for extracting func-tional (control/data flow) information fro...
Abstract—The generation of device drivers is a very time con-suming and error prone activity. All th...
IP core integration into an embedded platform implies the implementation of a customized device driv...
Plugging an IP core into an embedded platform implies the generation of a device driver complying wi...
This paper presents a correct-by-construction synthesis method for generating operating system based...
Transaction Level Modeling (TLM) is an emerging design practice forovercoming increasing design comp...
Transaction Level Modeling (TLM) is an emerging de-sign practice for overcoming increasing design co...
Abstract. We have separated the information required for HW/SW interface synthesis into three parts,...
Writing device drivers takes much time and requires effort because it needs knowledge of the target ...
Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complex...
One of the main critical tasks in a design flow based on Transaction Level Modeling (TLM) is the imp...
The arising complexity of modern system-on-chips (SoCs) makes the reuse of existent IP cores a key s...
Over the last two decades, chip design has been conducted at the register transfer (RT) Level using ...
With the rapid increase in the complexity of digital circuits, the design abstraction level has to g...
Due to the character of the original source materials and the nature of batch digitization, quality ...
In this paper, we present a technique for extracting func-tional (control/data flow) information fro...
Abstract—The generation of device drivers is a very time con-suming and error prone activity. All th...
IP core integration into an embedded platform implies the implementation of a customized device driv...
Plugging an IP core into an embedded platform implies the generation of a device driver complying wi...
This paper presents a correct-by-construction synthesis method for generating operating system based...
Transaction Level Modeling (TLM) is an emerging design practice forovercoming increasing design comp...
Transaction Level Modeling (TLM) is an emerging de-sign practice for overcoming increasing design co...
Abstract. We have separated the information required for HW/SW interface synthesis into three parts,...
Writing device drivers takes much time and requires effort because it needs knowledge of the target ...
Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complex...
One of the main critical tasks in a design flow based on Transaction Level Modeling (TLM) is the imp...
The arising complexity of modern system-on-chips (SoCs) makes the reuse of existent IP cores a key s...
Over the last two decades, chip design has been conducted at the register transfer (RT) Level using ...
With the rapid increase in the complexity of digital circuits, the design abstraction level has to g...
Due to the character of the original source materials and the nature of batch digitization, quality ...
In this paper, we present a technique for extracting func-tional (control/data flow) information fro...