Reduction of Leakage Power in Networks-on-Chip with Buffers Power-Gating

A NoC consists of a topology of interconnected switches, usually a regular one like a mesh. Processing elements and memories are connected to the switches. High-performance NoCs consume a relevant fraction of chip power and a large part of this power is consumed by network buffers. We report on our recent work on leakage power reduction of the SRAM buffers that make up the FIFO queues of a NoC switch. In particular we focus on reducing power of SRAM buffers that are not fully utilized. NoC traffic may present large spatial and temporal variations, and so not fully loaded NoC nodes can be reconfigured to save power. We assume that the SRAM buffers can be partitioned in banks and that each bank can be individually put in a low-power state by cutting its power supply via power MOSFETs, a technique termed power-gating