In this paper, we propose a combined solution that allows us to customize the architecture of internally partitioned SRAM macros according to the given application be executed. Energy savings with respect to monolithic memory configurations are above 40%, without access time violation
In high performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic ...
International audienceModern computing applications require more and more data to be processed. Unfo...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...
In this paper, we propose a combined solution that allows us to customize the architecture of intern...
Memory partitioning has proved to be a promising solution to reduce energy consumption in complex So...
Application-Specific Block-Enabled (ASBE) SRAMs represent a viable solution for reducing energy cons...
Memory-processor integration offers new opportunities for reducing the energy of a system. In the ca...
Memory-processor integration offers new opportunities for reducing the energy of a system. In the ca...
(c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Technology scaling results in significant increase of leakage currents in MOS devices due to which p...
A configurable dual-port SRAM macro-cell has been developed based on a commercial, 0.25 µm, 3 metal ...
International audienceIn order to minimize the energy consumed by the main memory in embedded system...
DoctorThis dissertation presents three case studies on the design of smart SRAM that is capable of ...
In high performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic ...
International audienceModern computing applications require more and more data to be processed. Unfo...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...
In this paper, we propose a combined solution that allows us to customize the architecture of intern...
Memory partitioning has proved to be a promising solution to reduce energy consumption in complex So...
Application-Specific Block-Enabled (ASBE) SRAMs represent a viable solution for reducing energy cons...
Memory-processor integration offers new opportunities for reducing the energy of a system. In the ca...
Memory-processor integration offers new opportunities for reducing the energy of a system. In the ca...
(c) 2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon ...
Technology scaling results in significant increase of leakage currents in MOS devices due to which p...
A configurable dual-port SRAM macro-cell has been developed based on a commercial, 0.25 µm, 3 metal ...
International audienceIn order to minimize the energy consumed by the main memory in embedded system...
DoctorThis dissertation presents three case studies on the design of smart SRAM that is capable of ...
In high performance Systems-on-Chip, leakage power consumption has become comparable to the dynamic ...
International audienceModern computing applications require more and more data to be processed. Unfo...
PosterDRAM vendors have traditionally optimized for low cost and high performance, often making desi...