An Adaptive Data Compression Scheme for Memory Traffic Minimization in Processor-Based Systems

This paper proposes a data compression scheme for minimizing memory traffic in processor-based systems. Data compression and decompression are performed on-the-fly on the cache-to-memory path, that is, uncompressed cache lines are compressed before they are written back to main memory, and decompressed when cache refills take place. The distinguishing feature of the presented solution is its ability of providing high memory traffic reductions without requiring data profiling information. In other words, thanks to the self-learning mechanism it implements, the proposed scheme performs very closely to special-purpose compression approaches, whose main limitation is their inapplicability when off-line data profiling is not feasible. Memory traffic reductions in the cache-to-memory path of a core-based system running standard benchmark programs are, on average, around 34%, and are thus close to those achievable with profile-driven compression