Design and implementation of a scalable multimedia processor

This work describes the design and implementation of a highly customisable multimedia processor. The proposed core has been developed with the goal of simplicity and effectiveness. Moreover, thanks to its soft-core nature, it is suited for being implemented over different physical layers. In particular, in this paper, an FPGA-oriented implementation is addressed. Additionally, this core can be configured to contain a different number of functional units depending on the specific application. In order to validate the proposed approach, three different configuration profiles have been fully implemented on a Xilinx Virtex XCV2000E FPGA