Energy efficient deep learning on FPGA using binary convolutional neural network

Deep convolutional neural networks (DCNNs) are widely used in fields such as artificial intelligence and computer vision. However, in computer vision, to provide state of the art results in image classification task for processing just one image, DCNNs need to perform billions of operations. Many deep learning applications demand low-power hardware devices. DCNNs require large computations so it is hard to utilize them on low-power embedded devices. This problem can be solved by efficient algorithm design and hardware constructs designed for the algorithm. By doing so, the competence of deep learning networks can be improved by faster prediction speed, lower power consumption, higher accuracy and smaller model size. This thesis focuses on efficiently optimizing deep learning algorithm on an FPGA using a neural network with binary weights and activations. This method significantly reduces the computations and memory requirement which makes it suitable to apply in embedded applications. Image classification task is performed to test this model on an FPGA