Pipeline FFT architecture implementation using Verilog HDL

In most of the Communication Systems the Fourier transform is the main concept to process the signals which are used in the system. Then the FFT/IFFT comes in to the picture for fast signal processing, but the FFT/IFFT has some delays present and area of the implementation is very large [1]. So we need to design an architecture which is optimized in terms of both delay and area. The Main Reason for the delay and complexity of the architecture due to the complex multiplications implementation present in the Fast Fourier Transform due to the twiddle factors ( ). Then the proposed pipeline architecture leads to decreasing of the complex multiplications [1]. But the delay is present in this architecture also. Here we propose Pipeline architecture which removes the complex multiplications using the twiddle factors. In this Pipeline architecture we are going to use the delay elements, switch elements and basic butterfly structure and the input data stream is divided in to two half streams and processing is done at the same time and output data stream will also be in two half data streams and here the number of complex multiplications will be reduced a lot which reduces the cost of implementation