Add to ORKGDue to fast growth of portable devices, power consumption and timing delays are the two important design parameters in high speed and low power VLSI design arena. In this paper we presents the comparison of single edge triggered static D flip-flop designs to show the benefit of power consumption ,delay and power delay product on the basis of area efficiency. Keywords: Single edge triggered flip-flops, super-threshold region, parasitic capacitance, transmission gat
The past few years, increasing difficulty in integration can be solved by low power, which is very i...
Abstract- The devices such as laptop, mobile phones and personal digital assistants (PDA) require lo...
In area of low power VLSI, switching activity of circuit node is of great concerned t...
Due to fast growth of portable devices, power consumption and timing delays are the two important de...
In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The ...
The increasing demand of portable applications motivates the research on low power and high speed ci...
The paper proposed a new design of static SET flip-flop for low power applications. In this work, co...
In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The ...
[[abstract]]In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETF...
In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design...
In Each and every electronic component, the Flip flop is the one of the major component in VLSI Low ...
In this paper, a double edge-triggered (DET), static SOI D flip-flop design suitable for low power a...
Due to increased demand of portable and battery operated devices, ultra-low power and high speed dev...
This paper enumerates a low power, high speed design of flip-flop having less number of transistors....
True single-phase clock (TSPC) rationale has discovered broad use in digital design. Initially as a ...
The past few years, increasing difficulty in integration can be solved by low power, which is very i...
Abstract- The devices such as laptop, mobile phones and personal digital assistants (PDA) require lo...
In area of low power VLSI, switching activity of circuit node is of great concerned t...
Due to fast growth of portable devices, power consumption and timing delays are the two important de...
In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The ...
The increasing demand of portable applications motivates the research on low power and high speed ci...
The paper proposed a new design of static SET flip-flop for low power applications. In this work, co...
In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The ...
[[abstract]]In this paper, a new low power and high speed CMOS double-edge triggered flip-flop (DETF...
In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design...
In Each and every electronic component, the Flip flop is the one of the major component in VLSI Low ...
In this paper, a double edge-triggered (DET), static SOI D flip-flop design suitable for low power a...
Due to increased demand of portable and battery operated devices, ultra-low power and high speed dev...
This paper enumerates a low power, high speed design of flip-flop having less number of transistors....
True single-phase clock (TSPC) rationale has discovered broad use in digital design. Initially as a ...
The past few years, increasing difficulty in integration can be solved by low power, which is very i...
Abstract- The devices such as laptop, mobile phones and personal digital assistants (PDA) require lo...
In area of low power VLSI, switching activity of circuit node is of great concerned t...