Array Multiplier using pMOS based 3T XOR Cell

This paper proposes a 3T XOR gate design consisting of pMOS transistors. This new design of XOR cell has been compared with existing 3T XOR design and significant improvement in PDP (Power-Delay Product) has been obtained. As an application of proposed XOR gate, a 2×2 array multiplier has been designed which also shows promising performance than existing one. All simulations are performed on 45nm standard model on Tanner EDA tool version 13.0. Keywords: 3T (3 transistor), XOR gate, 2×2 array multiplier and PDP (Power-Delay Product)