Improved single-phase PLL structure with DC-SOGI block on FPGA board implementation

Synchronization block which is used as a part of photovoltaic (PV) inverters control structure has a key impact on connectinginverters with grid. One of the most important parameters in the point of connection PV inverter and grid is phase angle between gridvoltage and inverter current. This angle determines the energy transfer between inverter and grid. Synchronization algorithms havedeveloped for very long time. At first, they were based on zero crossing grid voltage detection, while today complexed synchronizationalgorithms implemented on high performance digital board have been used. One of these synchronization structures is Phase LockedLoop – PLL. In this paper implementation of improved PLL structure is presented. This improved structure is special while it haspossibility of grid parameters estimation even if grid voltage has noise or DC offset. This DC offset from the grid in PLL structureusually entered via measurement and A/D conversion processor or may be generated due to temporary system faults. Appearance ofDC offset in measured grid voltage on the one hand prevents any estimation process of grid parameters and on the other hand alsodegrades reference sine signal at the output of PLL structure in PV inverters. This improved structure is designed in digital form andimplemented on FPGA digital board and experimental results of this implementation are presented. Obtained experimental resultsshow that the proposed PLL structure successfully solves important issue such is presence of DC offset in measured grid voltage