Host-Network Interface Architecture for Gigabit Communications

There are two complementary trends in the computer and communications fields. Increasing processor power and memory availability allow more demanding applications, such as scientific visualizations and imaging. Advances in network performance and functionality have the potential for supporting applications requiring high bandwidth communications. However, the bottleneck is increasingly in the host-network interface, and thus the ability to deliver high performance communications capability to applications has not kept up with the advance in computer and network speed. We have proposed a new architecture that meets these challenges, called Axon. The Axon thesis is that an essential requirement for the support of high performance distributed IPC is to provide a direct channel for object transfer between the communicating processes. Thus, this research centers on how to create an end-to-end pipeline to deliver this high bandwidth to applications. The goals are to develop a suitable architecture, determine the key issues and tradeoffs, and evaluate them as data rates scale beyond 1 Gbps. Novel aspects of this research include: an integrated design of hardware, operating systems, and communications protocols, stressing both performance and the required functionality for demanding applications; the proper division of hardware and software function; and reorganization of end-to-end protocols to take advantage of the increased functionality of the emerging high speed internetworks