Add to ORKGThis paper describes the design of the Packet Switch Element Chip, one of the components of a high speed broadcast packet switching network. The chip is a 2x2 switch element, from which a switch fabric of arbitrary size can be constructed. It is currently being implemented in 3um, CMOS technology
With the rapid development of optical communications, transport of data over fiber channel can now r...
[[abstract]]© 1990 Institute of Electrical and Electronics Engineers-The design of a large, multista...
This thesis illustrates the design of a single chip Asynchronous Transfer Mode (ATM) protocol switch...
This paper describes the design of the Packet Switch Element Chip, one of the components of a high s...
This paper describes the design of the PP3 packet processor chip. PP3 is one of the four component c...
This paper describes the design of the Packet Buffer Chip. Packet Buffers are FIFO queues used for b...
This paper describes the design of a Broadcast Translation Circuit chip. The Broadcast Translation C...
The broadcast packet network is a form of communications network based on high speed packet switches...
This paper describes a high performance packet switching network that can be used to provide voice, ...
It is the objective of this thesis to investigate a number of issues associated with building a sc...
This paper describes the design and prototype of a complete hardware system for high speed optical b...
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright...
To solve a performance bottle neck in random access LANs due to packet collisions and their resoluti...
Abstract. This paper addresses the design of an application-specific processor with emphasis on pack...
This paper describes an innovative packet-switched network architecture hardware prototype, designed...
With the rapid development of optical communications, transport of data over fiber channel can now r...
[[abstract]]© 1990 Institute of Electrical and Electronics Engineers-The design of a large, multista...
This thesis illustrates the design of a single chip Asynchronous Transfer Mode (ATM) protocol switch...
This paper describes the design of the Packet Switch Element Chip, one of the components of a high s...
This paper describes the design of the PP3 packet processor chip. PP3 is one of the four component c...
This paper describes the design of the Packet Buffer Chip. Packet Buffers are FIFO queues used for b...
This paper describes the design of a Broadcast Translation Circuit chip. The Broadcast Translation C...
The broadcast packet network is a form of communications network based on high speed packet switches...
This paper describes a high performance packet switching network that can be used to provide voice, ...
It is the objective of this thesis to investigate a number of issues associated with building a sc...
This paper describes the design and prototype of a complete hardware system for high speed optical b...
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright...
To solve a performance bottle neck in random access LANs due to packet collisions and their resoluti...
Abstract. This paper addresses the design of an application-specific processor with emphasis on pack...
This paper describes an innovative packet-switched network architecture hardware prototype, designed...
With the rapid development of optical communications, transport of data over fiber channel can now r...
[[abstract]]© 1990 Institute of Electrical and Electronics Engineers-The design of a large, multista...
This thesis illustrates the design of a single chip Asynchronous Transfer Mode (ATM) protocol switch...