Reduction of Clock Delays in VSLI Structures

With the growth in chip size and reduction in line width, delays in driving long lines have become increasingly important in determining overall chip level performance. In synchronous systems the proper distribution of the clock signal is critical in determining system throughput. This paper considers the problem of optimal driving clock lines. A general delay model is developed and applied to a clock tree where the path distances from the root node to each of the leaf nodes are all equal. This strategy reduces clock skew and increases clock rates. A tree delay model is developed and is used to determine the optimal number and placement of buffers within the tree so that the clock delay is minimized. AN example of a clock tree driving a synchronous crossbar network is provided, and minimum delay and corresponding number of buffers are indicated as a function of the minimum line width and network size. For a 64*64 network this minimization technique yielded an order of magnitude delay reduction over standard single exponential buffer usage