A novel process algebra is presented; algebraic expressions specify delay-insensitive circuits in terms of voltage-level transitions on wires. The approach appears to have several advantages over traditional state-graph and production-rule based methods. The wealth of algebraic laws makes it possible to specify circuits concisely and facilitates the verification of designs. Individual components can be composed into circuits in which signals along internal wires are hidden from the environment
Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, ...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Jan Tijmen Udding received the B.S. and M.S. degrees in mathematics, and the Ph.D. degree in compute...
Abstract. We introduce algebras capable of representing, detecting, identifying, and counting static...
A process algebra is given for specifying delay-insensitive processes. We show in two steps that exp...
This paper presents a new methodology to automatically synthesize asynchronous circuits from descrip...
A process algebra is given for specifying delay-insensitive processes. We show in two steps that exp...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
A process is a pair 〈 A, X 〉 in which A is a set of symbols (the alphabet) and X is a non-empty pref...
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed in...
Successful timing analysis of high-speed integrated circuits requires accurate delay computation. Ho...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
AbstractConsider a network N constructed from a set of modules interconnected by wires. Suppose that...
Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, ...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Jan Tijmen Udding received the B.S. and M.S. degrees in mathematics, and the Ph.D. degree in compute...
Abstract. We introduce algebras capable of representing, detecting, identifying, and counting static...
A process algebra is given for specifying delay-insensitive processes. We show in two steps that exp...
This paper presents a new methodology to automatically synthesize asynchronous circuits from descrip...
A process algebra is given for specifying delay-insensitive processes. We show in two steps that exp...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is ...
A process is a pair 〈 A, X 〉 in which A is a set of symbols (the alphabet) and X is a non-empty pref...
A case study in delay-insensitive circuit design is presented. A one bit wide stack is decomposed in...
Successful timing analysis of high-speed integrated circuits requires accurate delay computation. Ho...
Methods for the synthesis of asynchronous circuits from signal transition graphs (STGs) have commonl...
AbstractConsider a network N constructed from a set of modules interconnected by wires. Suppose that...
Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, ...
Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asyn...
Jan Tijmen Udding received the B.S. and M.S. degrees in mathematics, and the Ph.D. degree in compute...