Robust Real-time Automated Cardiac Remote Health Care Monitoring System-on-chip Architecture

Cardiovascular diseases healthcare monitoring systems have gained signi_cant importance in recent years owing to their tremendous challenge for portable personal health analysis. With the consideration of portable remote monitoring, it is necessary to develop the remote Cardiovascular Diseases (CVD) device having low form factor, consuming minimal power for the prolonged battery life and the device should be reliable enough to extract the signi_cant clinical features for the cardiovascular diseases classi_cation and prediction at an a_ordable cost. This thesis primarily focused on working in developing di_erent classi_cation techniques and integrating them to make a generic algorithm and develop the novel System-On-Chip (SoC) architecture in a low complex way by resource sharing concept. Thus the whole system can cover various ECG abnormalities and _nally come up with the prototype board which looks similar to as a smartphone at the patient end. The SoC architecture is designed using ARM Cortex M0+ for cardiac remote health monitoring which does process and classi_es the ECG signal, Cortex M0+ Processor based Cortex M0+ System Design Kit(CMSDK) is used for designing the SoC architecture. The proposed novel ARM CM0+ based SoC features the combination of proposed processing algorithms which is _ve folded modeling and implemented in CMSDK. After the data sensing, as a part of processing, _rstly the proposed Boundary Detection (BD) methodology is applied on the continuous _ltered ECG waveform to identify the start and end boundaries of individual ECG beats. Secondly, the proposed Feature Extraction (FE) methodology extracts the clinical features (amplitude, duration, polarity) of characteristic waves such as P-wave, QRS-complex, T-wave, and the interval features between the characteristic waves from each ECG beat. The third step involves in automatic detection of fragmented QRS (f-QRS) followed by identi_cation of various morphologies of the QRS complex. Compressing the ECG data using the proposed hybrid compression methodology and the compressed data is stored on the SoC itself is the fourth step. The compressed ECG data is transmitted either at regular intervals of half an hour or depends on the condition of Rule Engine (RE) output which is the _fth processing block of SoC. RE takes the outcome of BD, FE, and f-QRS as input and compares with the standard clinical values to classify the patient condition. If any abnormality is detected from the RE block, the communication module will be triggered and the compressed ECG data is transmitted by the device to a centralized facility via cloud where a doctor or a high-performance computational unit is present. The compressed ECG data is decompressed at the doctor end for further prediction of ECG abnormality using Phase Space Reconstruction based detection and classi_cation to predict the life-threatening condition using the localized features (PR interval, QRS complex and QT interval) of the ECG signal and takes necessary action if the condition of the patient is critical. Hardware and software partitioning of processing methodologies is done for the implementation of SoC, where BD, FE and f-QRS methodologies are coded in software as a part of SoC and the hybrid compression block is considered as an APB hardware peripheral to the ARM CM0+ processor based CMSDK. To validate the SoC design, the ECG data is taken from the publically available database PTBDB, MITDB, CSEDB and from the in-house developed 12 lead ECG acquisition board with ADC con_guration of 1 KHz sampling frequency and each sample of 16-bit data. The veri_cation of the entire SoC design is done using VCS of Synopsys tool, the hexadecimal _le of C code (.hex) which uses CMSIS standard header _les of the CMSDK is generated using DS5 Compiler. The SoC design has been implemented in UMC 180nm technology and operated at 1 MHz with V dd 1.8V, resulting in power consumption of 14.66 mW and occupying the area 13.767 mm2 are calculated using the Synopsys design compiler tool. The entire design is prototyped on Virtex7 FPGA and the utilization of the resources are tabulated in the result section