On chip implement of deadlock avoidance in wormhole networks

This thesis gives a detailed description of the Application Specific Integrated Circuit (ASIC) design to avoid deadlocks in Wormhole Networks. Deadlock avoidance is the most critical issue while considering wormhole networks and should be avoided by any routing protocol and algorithm. A novel architecture for the Turn Prohibition Based Routing (TPBR) protocol has been proved to be efficient and was developed as a part of this work. This architecture for implementing the algorithm is divided into three parts. The first part determines the order of selccuon of the nodes, in the network to run the algorithm. The second part deals with the prohibition of the turns through the node which might possibly create a deadlock. The third part constructs a routing table, which will have the route from a source to a destination, considering the prohibited, turns into account. A VHDL model was developed and simulated using IEEE numeric-std package for this architecture. This model was synthesized with Cadence tools and the post synthesis simulations verified the functionality of the architecture. The physical design was created using the standard gate cell libraries and implemented in 0.35-micron CMOS technology