Formation and characterization of n/p shallow junctions in sub-micron MOSFETs

Semiconductors are the burgeoning industries in today\u27s information age. Silicon based microelectronic devices are shrinking day-by-day in accord with the scaling dimensions reported by the International Technology Roadmap for Semiconductors (ITRS). There have been many semiconductor models and simulation programs constantly keeping pace with the continuously evolving scaling dimensions, process technology, performance and cost. Electrical characterization plays a vital role in determining the electrical properties of materials and device structures. Silicon based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) forms the basis of Complimentary Metal Oxide Semiconductor (CMOS) circuits. Today\u27s aggressive scaling approaches in silicon Integrated Circuit (IC) technology require ultra shallow junctions in MOSFETs. The objective of this thesis is to study the leakage current in n/p shallow junctions and to correlate them with process steps required for the formation of shallow junctions. The leakage current measurements were performed by utilizing three-point probe method, which is one of the popular techniques used in the semiconductor industry. Apart from n/p shallow junctions, experiments have been performed on p/n shallow junctions. Finally, comparison of the leakage current measurements has been made. The comparison takes into account the implant variables and post-implant annealing steps that have been deployed in the fabrication of shallow junctions