FeFET Process Integration and Characterization

Hafnium oxide-based ferroelectrics are gaining popularity in the field of non-volatile memory due to their superior scalability in reference to traditional, lead-based ferroelectric materials and their compatibility with CMOS technology. Ferroelectric field-effect transistors (FeFETs) incorporate such materials in their gate stack, providing for bi-stable transfer characteristics and threshold voltages, which can be interpreted as storage values of 0 or 1. The difference between these threshold voltages is a FeFET figure of merit, referred to as the memory window (MW) of the device. A process for fabricating n-channel FeFETs in-house at RIT has been developed, incorporating atomic layer deposition (ALD) of Al:HfO2 and CMOS processing techniques. Test results of the first lot show signs of improper source/drain formation, evidenced in part by high off-state leakage and a poor on- to off-state current ratio; the root cause of improper formation is still being investigated. Nevertheless, ferroelectric behavior has been observed. Figure 1 shows the transfer characteristics of a representative FeFET from the first lot with a memory window of approximately 150mV. This result is comparable to that obtained from a device with a similar ferroelectric film in literature. The impact of threshold adjustment implantation on the transfer characteristics and memory window of the devices was also investigated, and ultimately found to shift both transfer curves of a given device without degrading memory window. To revive the current devices, monolayer doping (MLD) techniques will be employed to recreate source and drain regions, and devices will be retested; a new device lot will follow