The goal of this project was to fabricate MOSFETs on InGaAs with an Al2O3 gate dielectric deposited with ALD. The initial structure of the device was planned out, the process was designed, and then each step of the process was characterized prior to the fabrication of the devices. The devices were fabricated, and then electrically tested. Each of the separate processes were shown to be repeatable and accurate. Errors with design rules in the mask lay- out led to shorting of the devices from source to drain, however the gate was found to be electrically isolated
As the Moore\u27s Law push device scaling to a fundamental physical limit, alternatives have been at...
textSi complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuo...
The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxi...
Lacking a suitable gate insulator, practical GaAs metal-oxide-semiconductor field-effect transistors...
textThe performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs...
As the Si CMOS roadmap for scaling approaches its fundamental physics limits, alternatives have been...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
AbstractIn this paper, we investigate the scaling and carrier transport behavior of sub-100nm In0.7G...
This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semi...
As Silicon complementary-oxide-semiconductor (CMOS) devices scale into the sub-22nm regime, severe s...
The state-of-the-art knowledge about the passivation as well as the historical advancements for real...
The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a ...
[[abstract]]A GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) with thin Al2O3 gate d...
High-performance inversion-type enhancement-mode n-channel In0.65Ga0.35As metal-oxide-semiconductor ...
With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel ...
As the Moore\u27s Law push device scaling to a fundamental physical limit, alternatives have been at...
textSi complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuo...
The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxi...
Lacking a suitable gate insulator, practical GaAs metal-oxide-semiconductor field-effect transistors...
textThe performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs...
As the Si CMOS roadmap for scaling approaches its fundamental physics limits, alternatives have been...
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Comp...
AbstractIn this paper, we investigate the scaling and carrier transport behavior of sub-100nm In0.7G...
This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semi...
As Silicon complementary-oxide-semiconductor (CMOS) devices scale into the sub-22nm regime, severe s...
The state-of-the-art knowledge about the passivation as well as the historical advancements for real...
The first inversion-mode gate-all-around (GAA) III-V MOSFETs are experimentally demonstrated with a ...
[[abstract]]A GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) with thin Al2O3 gate d...
High-performance inversion-type enhancement-mode n-channel In0.65Ga0.35As metal-oxide-semiconductor ...
With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel ...
As the Moore\u27s Law push device scaling to a fundamental physical limit, alternatives have been at...
textSi complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuo...
The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxi...