Add to ORKGThe following experiment was completely in order to analyze and quantify the influence implantation dose and post implant anneal conditions have on the source and drain regions of a typical transistor. A DOE experiment was designed to investigate three different variations in each the implantation dose and post implant anneal temperatures of the source and drain regions of the advanced CMOS process transistor at RIT. Electrical characterization was used to obtain quantifiable results for each experimental variation. The experiment was successful in manufacturing a complete analysis for variations in the source and drain doping profile
The incorporation of nitrogen in silicon has been shown to retard the oxidation growth rate. The pre...
A study on the influence of phosphorus implanted source/drain features on the off-state performance ...
In this paper, we investigate the influence of process parameters like HALO and Source/Drain (S/D) ...
This project was an investigation into transistor development in areas of implanted wells and source...
The formation of shallow junctions in the source and drain regions is a major challenge to the conti...
In the last years a lot of effort has been directed in order to reduce silicon defects eventually fo...
The objective of this project is to investigate the electrical characteristics of Buried Channel PMO...
A test chip has been designed for experimental use in determining and maintaing the operation of an ...
The relative sensitivity of the CMOS device parameters on various process steps are evaluated throug...
Producción CientíficaIon implantation continues being the dominant technique to introduce dopants in...
As CMOS device dimensions continue to shrink below 200nm, one of the major limiting factors in scali...
Silicon wafer has been implanted with 200keV14N+ ions to a dose of 0.75 x 10 18N+ /cm2 at a temperat...
Contains reports on four research projects.Lincoln Laboratory (Purchase Order DDL-B187)United States...
A successful test layout for S-parameter analysis was demonstrated. Process characterization accompl...
The low-temperature annealing kinetics of ion implanted silicon is a critical factor worthy of consi...
The incorporation of nitrogen in silicon has been shown to retard the oxidation growth rate. The pre...
A study on the influence of phosphorus implanted source/drain features on the off-state performance ...
In this paper, we investigate the influence of process parameters like HALO and Source/Drain (S/D) ...
This project was an investigation into transistor development in areas of implanted wells and source...
The formation of shallow junctions in the source and drain regions is a major challenge to the conti...
In the last years a lot of effort has been directed in order to reduce silicon defects eventually fo...
The objective of this project is to investigate the electrical characteristics of Buried Channel PMO...
A test chip has been designed for experimental use in determining and maintaing the operation of an ...
The relative sensitivity of the CMOS device parameters on various process steps are evaluated throug...
Producción CientíficaIon implantation continues being the dominant technique to introduce dopants in...
As CMOS device dimensions continue to shrink below 200nm, one of the major limiting factors in scali...
Silicon wafer has been implanted with 200keV14N+ ions to a dose of 0.75 x 10 18N+ /cm2 at a temperat...
Contains reports on four research projects.Lincoln Laboratory (Purchase Order DDL-B187)United States...
A successful test layout for S-parameter analysis was demonstrated. Process characterization accompl...
The low-temperature annealing kinetics of ion implanted silicon is a critical factor worthy of consi...
The incorporation of nitrogen in silicon has been shown to retard the oxidation growth rate. The pre...
A study on the influence of phosphorus implanted source/drain features on the off-state performance ...
In this paper, we investigate the influence of process parameters like HALO and Source/Drain (S/D) ...