Monolithic integration of CMOS and MEMS is quickly proving to be a viable asset to current complex structures. However, synthesis of these technologies has proven to have multiple processing obstacles. Depending on the method used to create these devices, the hurdles include the effects of silicon etching and high temperature processing. For this experiment, previously processed CMOS wafers were obtained and a trench was etched into the silicon. “Family of curves” plots of the working CMOS wafers were taken before and after processing to study any changes in ID. Results have shown that the processing of this integration will effect the family of curve plots, however this was not concluded as a result of a small sample size
This work reports on studies and the fabrication process development of micromechanical silicon-on-i...
We report a CMOS compatible bulk micromachining method for the integration of high-aspectratio singl...
Microdefect distribution in a monocrystalline silicon wafer is identified by saturating the wafer wi...
A modular approach, based on work done at Sandia National Laboratories, for the monolithic integrati...
Recently, a great deal of interest has developed in manufacturing processes that allow the monolithi...
In this work, compatible CMOS-MEMS process with surface micromachining is investigated. Surface micr...
A MEMS-first fabrication process for integrating CMOS circuits with polysilicon micromechanical str...
Lecture describing the lithography, CMOS fabrication of an inverter to demonstrate Integrated Micro-...
The monolithic integration of micromechanical devices with their controlling electronics offers pote...
A novel modular fabrication process for bulk integrated single-crystal-silicon microstructures desig...
This work reports on studies and the fabrication process development of micromechanical silicon-on-i...
A new process kit for a SPTS Pegasus DRIE Si-Etch tool has been developed and tested for several dif...
Reactive Ion Etching (RIE) is an important process widely used in the fabrication of micro-electro m...
A novel modular fabrication process for bulk integrated single-crystal-silicon microstructures desig...
Long the dominant method of wafer planarization in the integrated circuit (IC) industry, chemical-me...
This work reports on studies and the fabrication process development of micromechanical silicon-on-i...
We report a CMOS compatible bulk micromachining method for the integration of high-aspectratio singl...
Microdefect distribution in a monocrystalline silicon wafer is identified by saturating the wafer wi...
A modular approach, based on work done at Sandia National Laboratories, for the monolithic integrati...
Recently, a great deal of interest has developed in manufacturing processes that allow the monolithi...
In this work, compatible CMOS-MEMS process with surface micromachining is investigated. Surface micr...
A MEMS-first fabrication process for integrating CMOS circuits with polysilicon micromechanical str...
Lecture describing the lithography, CMOS fabrication of an inverter to demonstrate Integrated Micro-...
The monolithic integration of micromechanical devices with their controlling electronics offers pote...
A novel modular fabrication process for bulk integrated single-crystal-silicon microstructures desig...
This work reports on studies and the fabrication process development of micromechanical silicon-on-i...
A new process kit for a SPTS Pegasus DRIE Si-Etch tool has been developed and tested for several dif...
Reactive Ion Etching (RIE) is an important process widely used in the fabrication of micro-electro m...
A novel modular fabrication process for bulk integrated single-crystal-silicon microstructures desig...
Long the dominant method of wafer planarization in the integrated circuit (IC) industry, chemical-me...
This work reports on studies and the fabrication process development of micromechanical silicon-on-i...
We report a CMOS compatible bulk micromachining method for the integration of high-aspectratio singl...
Microdefect distribution in a monocrystalline silicon wafer is identified by saturating the wafer wi...