Add to ORKGPolysilicon emitter vertical NPN transistors were fabricated in an attempt to create devices with very high current gains and high forward Early voltages. TMA SUPREM-3 simulations were used to optimize the process to obtain emitter junction depths of 0.05 and 0.08um. Final emitter junction depths of 0.1um, or less, were measured. High current gains were not achieved, due to high base doping
It was demonstrated that the common emitter current gain of bipolar transistors could be improved by...
The fabrication of the very high speed polysilicon emitter bipolar transistor and circuit with doubl...
An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CM...
Polysilicon emitters are prevalent in today's advanced B iCMOS processes. Electrical and materi...
A new method was presented in this article to explain high current gain of polysilicon emitter trans...
Silicon bipolar transistors have been fabricated with arsenic implanted or phosphorous diffused poly...
A new method was presented in this article to explain high current gain of polysilicon emitter trans...
A chip was designed containing lateral bipolar PNP devices with base widths ranging from four to ten...
This thesis describes the results of an experimental and theoretical study of the physics of polysil...
The recent developments in rapid thermal processing in the past several years have shown it to have ...
This thesis investigates the use of in-situ phosphorus doped polysilicon emitter contacts in deep su...
The development of integrated circuits toward high voltages introduce difficult compromises in regar...
grantor: University of TorontoConventional RF silicon bipolar transistors have a major lim...
A new program, BETA, will calculate a one-dimensional vertical transistor current gain using a modif...
In a self-aligned double polysilicon bipolar junction transistor (BJT) process, the emitter window i...
It was demonstrated that the common emitter current gain of bipolar transistors could be improved by...
The fabrication of the very high speed polysilicon emitter bipolar transistor and circuit with doubl...
An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CM...
Polysilicon emitters are prevalent in today's advanced B iCMOS processes. Electrical and materi...
A new method was presented in this article to explain high current gain of polysilicon emitter trans...
Silicon bipolar transistors have been fabricated with arsenic implanted or phosphorous diffused poly...
A new method was presented in this article to explain high current gain of polysilicon emitter trans...
A chip was designed containing lateral bipolar PNP devices with base widths ranging from four to ten...
This thesis describes the results of an experimental and theoretical study of the physics of polysil...
The recent developments in rapid thermal processing in the past several years have shown it to have ...
This thesis investigates the use of in-situ phosphorus doped polysilicon emitter contacts in deep su...
The development of integrated circuits toward high voltages introduce difficult compromises in regar...
grantor: University of TorontoConventional RF silicon bipolar transistors have a major lim...
A new program, BETA, will calculate a one-dimensional vertical transistor current gain using a modif...
In a self-aligned double polysilicon bipolar junction transistor (BJT) process, the emitter window i...
It was demonstrated that the common emitter current gain of bipolar transistors could be improved by...
The fabrication of the very high speed polysilicon emitter bipolar transistor and circuit with doubl...
An NPN bipolar transistor process was designed and fabricated for incorporation with RIT’s N well CM...