Add to ORKGA dry etch S1O2 process was optimized using the Plasmatrac 2406 RIE etcher at RIT, while maintaining selectivity to polysilicon and photoresist. The optimized process had Power of 350 Watts, Pressure of 127 mTorr, C2F6 of 60 sccm, and CHF3 of 171 sccm; This provided an oxide to poly selectivity of 5.5:1 with an oxide slope of 60°
Planar-junction, 1 mm x 1 mm, p+/n/n+ silicon solar cells, both with and without a textured surface,...
A double level polysilicon self-aligned PMOS process was used to fabricate an integrator circuit usi...
The aim of this project is to develop a dry etching process that could be utilized to realize high a...
A Si3N4 etch process using a Plasmatherm 2406 etcher and SF6 was determined. RS1/Discover was used t...
As transistors have decreased in size and increased in packing density, a need has arisen for an alt...
Silicon Nitride (Si3N4) sacrificial replacement gate were fabricated using the nitride cast method. ...
The creation of MANN files, generated by computer programs, to produce other than rectangular featur...
A study has been performed to determine the optimum surface treatment to adhere an aluminum hard mas...
Resolution capability of a GCA Mann 4800 DSW Stepper was improved using a bilayer photoresist scheme...
The effect of surface cleaning and passivation techniques on the reverse bias saturation current Jo ...
This project dealt with the design and installation of a TCA bubbler system. Considerations for safe...
The effects of an n-type and p-type doped polysilicon gate fabricated over both an n-type and p-type...
Thermally actuated micromirrors were fabricated to demonstrate a CMOS compatible surface micromachin...
The objective of this project was to investigate the possibility of producing array of microplasma, ...
A four bit microprocessor’s layout was drawn on an Apollo workstation using MOSIS two lambda design ...
Planar-junction, 1 mm x 1 mm, p+/n/n+ silicon solar cells, both with and without a textured surface,...
A double level polysilicon self-aligned PMOS process was used to fabricate an integrator circuit usi...
The aim of this project is to develop a dry etching process that could be utilized to realize high a...
A Si3N4 etch process using a Plasmatherm 2406 etcher and SF6 was determined. RS1/Discover was used t...
As transistors have decreased in size and increased in packing density, a need has arisen for an alt...
Silicon Nitride (Si3N4) sacrificial replacement gate were fabricated using the nitride cast method. ...
The creation of MANN files, generated by computer programs, to produce other than rectangular featur...
A study has been performed to determine the optimum surface treatment to adhere an aluminum hard mas...
Resolution capability of a GCA Mann 4800 DSW Stepper was improved using a bilayer photoresist scheme...
The effect of surface cleaning and passivation techniques on the reverse bias saturation current Jo ...
This project dealt with the design and installation of a TCA bubbler system. Considerations for safe...
The effects of an n-type and p-type doped polysilicon gate fabricated over both an n-type and p-type...
Thermally actuated micromirrors were fabricated to demonstrate a CMOS compatible surface micromachin...
The objective of this project was to investigate the possibility of producing array of microplasma, ...
A four bit microprocessor’s layout was drawn on an Apollo workstation using MOSIS two lambda design ...
Planar-junction, 1 mm x 1 mm, p+/n/n+ silicon solar cells, both with and without a textured surface,...
A double level polysilicon self-aligned PMOS process was used to fabricate an integrator circuit usi...
The aim of this project is to develop a dry etching process that could be utilized to realize high a...